1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit for driving a liquid crystal panel. More particularly, the invention relates to a semiconductor integrated circuit for a liquid crystal panel outputting an analog gradation voltage for the liquid crystal display on the basis of a digital image data, a gradation wiring for a display, a driver for the liquid crystal display and a stress test method.
2. Description of the Related Art
FIG. 21 is an illustration of the a construction of conventional liquid crystal display apparatus. The liquid crystal apparatus includes a thin film transistor (TFT) liquid crystal panel PNL and a semiconductor integrated circuit 40 for driving the liquid crystal panel PNL. The semiconductor integrated circuit 40 includes a data latch portion LT, a selector portion SEL, an operational amplifier portion OP and an output switching portion SW. In the data latch portion LT, 2×m in number of data latches LT1 to LT4 are arranged in horizontal direction. In the selector portion SEL, 2×m in number of selectors SELL to SEL4 are arranged in horizontal direction. In the operational amplifier portion OP, 2×m in number of operational amplifiers OP1 to OP4 are arranged in horizontal direction. In the output switching portion SW, a m in number of output switches SW1 and SW2 are arranged in horizontal direction.
In the semiconductor integrated circuit 40, if the number of outputs is 384, for example, the number m becomes 192. It should be noted that, in FIG. 21, reduced number of the components arranged in horizontal direction are illustrated for simplification of illustration.
To the data latch portion LT, data latching lines arranged immediately thereabove are connected via wiring contact portions 1 (shown by black dot ●). Negative data latches LT1 and LT3 and positive data latches LT2 and LT4 are arranged alternately in number of 2×m in horizontal direction. The negative data latches LT1 and LT3 receive and hold externally input a n bit (6 bits in case of 64 level gradation) digital image data for generating a negative analog gradation voltage of a predetermined gradation level. The positive data latches receive and hold externally input n bit digital image data for generating a position analog gradation voltage.
In the selector portion SEL, negative selectors SELL and SEL3 and positive selectors SEL2 and SEL4 are arranged alternatively in number of 2×m in horizontal direction. The negative selectors SELL and SEL3 are formed with N-channel MOS transistors, and the positive selectors SEL2 and SEL4 are formed with P-channel MOS transistors. In case of 64 level gradation, for example, 64×2 positive and negative gradation voltage lines LN are arranged immediately above the selectors SELL to SEL4. To the negative selectors SEL1 and SEL3, 64 negative gradation voltage lines LN are connected via the wiring contact portions 1, and to the positive selectors SEL2 and SEL4, 64 positive gradation voltage lines LN are connected via the wiring contact portions 1.
The negative selectors SEL1 and SEL3 select the negative analog gradation voltage of a given gradation level depending upon the digital image data held by the data latches LT1 and LT3 on the basis of the negative analog gradation voltage in a range from 6V to 0V generated on the negative gradation voltage lines LN, for example. The positive selectors SEL2 and SEL4 select the positive analog gradation voltage of a given gradation level depending upon the digital image data held by the data latches LT1 and LT3 on the basis of the positive analog gradation voltage in a range from 6V to 12V generated on the positive gradation voltage lines LN, for example.
In the operational amplifier portion OP, negative operational amplifiers OP1 and OP3 and position operational amplifiers OP2 and OP4 are arranged alternately in number of 2×m in horizontal direction. The negative operational amplifiers OP1 and OP3 amplify and output the negative analog gradation voltages selected by the negative selectors SEL1 and SEL3. The positive operational amplifiers OP2 and OP4 amplify and output the positive analog gradation voltages selected by the positive selectors SEL2 and SEL4.
In the output switch portion SW, the output switches SW1 and SW2 are arranged in number of m in horizontal direction. The output switch SW1 switches and outputs either the negative analog gradation voltage output from the negative operational amplifier OP1 and the positive analog gradation voltage output from the positive operational amplifier OP2 by switching a signal path between straight and cross, to the liquid crystal panel PNL. The output switch SW2 switches and outputs either the negative analog gradation voltage output from the negative operational amplifier OP3 and the positive analog gradation voltage output from the positive operational amplifier OP4 by switching a signal path between straight and cross, to the liquid crystal panel PNL. The liquid crystal panel PNL is driven each pixel of three colors of red, blue and green by predetermined gradation voltages for respective colors for liquid crystal display.
The semiconductor integrated circuit 40 is formed into a rectangular shape having greater length 24 in horizontal direction since 2×m sets (e.g. 384 sets) of columns, in which the data latch portion LT, the selector portion SEL and the operational amplifier portion OP are aligned vertically, are aligned in horizontal direction. For example, the length 24 in horizontal direction is approximately 15 mm and a length in vertical direction is approximately 2 mm. Since this semiconductor integrated circuit 40 has relative large area, development of the semiconductor integrated circuit 40 having smaller area has been demanded. Particularly, shortening of the horizontal length of the semiconductor integrated circuit 40 is strongly demanded.
On the other hand, in the portion immediately above the negative selectors SEL1 and SEL3, while the negative gradation voltage lines LN are connected to the negative selectors SEL1 and SEL3 via the wiring contact portions 1, the positive gradation voltage lines LN are not connected to the negative selectors SEL1 and SEL3 to wastefully leave the region where the positive gradation voltage lines are arranged (hatched region in the drawing) as non-use regions 2. Similarly, in the portion immediately above the positive selectors SEL2 and SEL4, wasteful non-use regions 2 are left.
On the other hand, since the negative selectors SELL and SEL3 formed with N-channel MOS transistors and the positive selectors SEL2 and SEL4 formed with P-channel MOS transistors are arranged alternately, it is required to provide a certain distance 23 between the selectors of mutually different channel type. This inherently require the longer length 24 of the semiconductor integrated circuit 40 in horizontal direction than necessary.
FIG. 22 is a wire diagram of a gradation voltage generating portion in a driver for the liquid crystal display in the prior art. The gradation voltage generating portion has reference voltage input terminals (IC pads) V1 to V9, a ladder resistor R and a gradation wiring WW. The gradation wiring WW can be divided into a front half gradation wiring WA and a rear half gradation wiring WB.
The gradation wiring WW includes sixty-four gradation wiring corresponding to sixty-four gradation levels for example, in practice. However, the following discussion will be given for the case where 33 gradation wiring W1 to W33 are present for simplification of illustration. Between respective gradation wiring of the gradation wiring W1 to W33, ladder resistors R are connected. The input terminal V1 is connected to the gradation wiring W1. The input terminal V2 is connected to the gradation wiring W5. The input terminal V3 is connected to the gradation wiring W9. The input terminal V4 is connected to the gradation wiring W13. The input terminal V5 is connected to the gradation wiring W17. The input terminal V6 is connected to the gradation wiring W21. The input terminal V7 is connected to the gradation wiring W25. The input terminal V8 is connected to the gradation wiring W29. The input terminal V9 is connected to the gradation wiring W33.
The gradation wiring W1 to W33 are connected to the not shown liquid crystal panel PNL for driving the latter with the gradation voltages supplied therefrom. Discussion will be given for a driving method of the liquid crystal panel PNL. It is assumed that 0V is applied to the input terminal V1 and 6V is applied to the input terminal V9. On the other hand, to the input terminals V2 to V8, a voltage interpolating between 0v to 6V are applied. Then, voltages generated in the gradation wiring W1 to W33 are divided by respective ladder resistors R. By this, voltages between 0V to 6V, for which y correction is operation and effected, are output from the gradation wiring W1 to W33 are output. Then, by applying the one of the voltage selected among the gradation wiring W1 to W33 depending upon the image data, to the liquid crystal panel PNL, the liquid crystal can be driven.
Each individual gradation wiring in the gradation wiring W1 to W33 is connected to the gradation wiring via the ladder resistor R. It is possible that a foreign matter (dust) penetrates between individual gradation wiring in a fabrication process of the driver for the liquid crystal display. When the foreign matter penetrates between individual gradation wiring, shorting between the between individual gradation wiring can be caused to make if impossible to output the normal gradation voltage from the gradation wiring W1 to W33. If complete shorting is caused between the between individual gradation wiring, it can be easily found as faulty product of the driver for the liquid crystal display in an inspection process.
However, even when the foreign matter penetrates between the between individual gradation wiring, it is possible not to cause complete shorting between the between individual gradation wiring. In such case, it becomes difficult to find failure in the inspection process to possibly ship the faulty product of the driver for the liquid crystal display. In such case, the condition of the foreign matter between the between individual gradation wiring can be varied while used by the user to cause difficulty in outputting the normal gradation voltage for occurrence of failure. If the normal gradation voltage is not output, line defect can be caused in pixel display on the liquid crystal panel PNL.
In order to avoid such program, a stress test has been performed upon inspection of the driver for the liquid crystal display. In the stress test, at first, a stress voltage application process is performed, and subsequently, the inspection process is performed.
Discussion will be given for the stress voltage application process. In the stress voltage application process, at first, a 12V stress voltage (maximum rated voltage), for example, is applied between the input terminals V1 and V2. The 12V stress voltage is also applied between the input terminals V2 and V3, for example. Similarly, between the terminals of the input terminals V3 to V9, the stress voltage is applied, respectively. For example, foreign matter is present between the between individual gradation wiring, insulation failure between the between individual gradation wiring elicits by application of the stress voltage.
After application of the stress voltage, the inspection process is performed. In the inspection process, similarly to normal driving of the liquid crystal panel PNL, 0V is applied to the input terminal V1, for example, and 6V is applied to the input terminal V9, for example, and voltages between 0 to 6V are applied to the input terminals V2 to V8. Then, output voltages of each individual gradation wiring W1 to W33 is measured. If the output voltage thus measured does not fall within a range of predetermined values, the driver for the liquid crystal display is rejected as the faulty product.
However, in the foregoing stress voltage application process, since 12V of the stress voltage is applied between the gradation wiring W1 and W5, low voltage in the extent of about 3V (=12V÷4) is only applied between the gradation wiring W1 and adjacent gradation wiring W2. Namely, it has not been possible to apply sufficiently high stress voltage between the individual gradation wiring. As a result, detection ratio of the insulation failure between the gradation wiring has been relatively low.
On the other hand, in the stress voltage application process, at first, the stress voltage is applied between the input terminals V1 and V2. Then, the stress voltage is applied between the input terminals V2 and V3. Similarly, the stress voltage is applied between the input terminals V3 to V9 sequentially. Therefore, the voltage application process has to be repeated for eight times to take long period in the stress voltage application process.